This invention is in the field of audio amplifiers, and is more specifically directed to reduction of harmonic distortion in class D audio amplifiers.
Class D output amplifiers are now commonplace in modern digital audio systems, as well as in other systems that drive output loads with signals generated from digital signal processing. As known in the art, class D output amplifiers include half-bridge and full-bridge push-pull output stages that are driven digitally, for example by way of pulse-width modulation (PWM). At sufficiently high PWM frequencies, class D amplifiers can drive output loads, such as audio speakers, at precision and fidelity equal to conventional analog output stages, and at high output power levels.
In the audio field, as well as in other applications, a common measure of output fidelity is total harmonic distortion (THD). The conventional definition of THD is the ratio of the sum of the powers of all harmonic frequencies above the fundamental output frequency, to the power at the fundamental frequency itself. Other somewhat equivalent definitions express THD as a ratio of the sum of the harmonic amplitudes (square root of the sum of the harmonic powers) to the amplitude of the fundamental. THD is typically expressed as a percentage, or in decibels (dB). Distortion is exhibited, in the time domain, by deviations from a pure sinusoid at the output load.
Filterless class-D output amplifiers are especially susceptible to THD at low output levels, which correspond to low duty cycles in the PWM domain. FIG. 1 illustrates a conventional filterless class D output amplifier 2 that has this susceptibility. Amplifier 2 has a conventional full-bridge (or “H-bridge”) output in this example, with both sides of load 11 driven by a separate push-pull output stage. Because amplifier 2 is a class D amplifier, the output energy applied to load 11 will be defined by the duty cycle at which a differential voltage is applied across load 11. The push-pull output stages essentially apply a rail-to-rail output swing.
Integrating differential amplifier 4 receives a differential input signal to amplifier 2, across its nodes IN+, IN−, and produces a differential output signal at nodes P_IN, N_IN. Integration is accomplished by capacitive feedback from the outputs of differential amplifier 4 to its inputs; resistive feedback via resistors 3P, 3N from the output of the H-bridge is also applied in the conventional manner. The voltage at node P_IN will control the drive applied to node P at one side of load 11, while the voltage at node N_IN will control the drive applied to node N at the opposite side of load 11. The P-side drive circuit includes comparator 6P, which compares the positive side output P_IN from integrating differential amplifier 4 to a ramp or triangle reference waveform produced by reference waveform generator 5, thus effectively converting the level on line P_IN to a pulse-width modulated signal at the frequency of the reference waveform. Typically, the frequency established by the reference waveform (i.e., the PWM frequency) is much higher than the highest frequency of interest in the differential input signal, such that the differential input signal level at nodes IN+, IN− is essentially constant within a given single PWM cycle. The pulsed output of comparator 6P is applied to deglitch function 8P, which filters timing glitches from the pulsed signal in the conventional manner. Dead-time drive circuit 9P converts the pulsed output from comparator 6P into high-side drive signal P_HS and low-side drive signal P_LS, and enforces a “dead time” at transitions of the output signal. During the dead time, both of the pull-up and pull-down devices P_PU and P_PD are held off to ensure that both are not turned on at the same time, which would result in inefficient and potentially damaging rail-to-rail crowbar current through the output stage. Pull-up output transistor P_PU is, in this example, an n-channel MOS transistor with its drain at the Vdd power supply voltage and its source at node P; pull-down output transistor P_PD is also an re-channel MOS transistor, and has its drain at node P and its source at ground. High-side drive signal P_HS from drive circuit 9P drives the gate of pull-up transistor P_PU and low-side drive signal P_LS drives the gate of pull-down transistor P_PD. Node P is connected to load 11.
The N-side circuitry of amplifier 2 includes comparator 6N, deglitch circuit 8N, dead-time drive circuit 9N, and a push-pull output stage of pull-up transistor N_PU and pull-down transistor N_PD, all connected in similar manner as the corresponding functions in the high-side circuitry of amplifier 2. However, as evident from FIG. 1 and as known in the art, the operational difference between the P-side and N-side drive circuits 9P, 9N in amplifier 2 stems from the differential voltage at the output of integrating differential amplifier 4. For example, during positive-polarity half-cycles of a sinusoidal input signal, the differential voltage at input nodes IN+, IN− is amplified by integrating differential amplifier 4 to a positive polarity differential signal at nodes P_IN, N_IN. This causes node P_COMP at the output of comparator 6P to be driven high earlier and for a longer pulse width than node N_COMP at the output of comparator 6N, because node P_IN is at a higher voltage than node N_IN during positive half-cycles. Accordingly, during a positive half-cycle of the input signal, there will be some period within each PWM period (i.e., the period of the ramp from generator 5) during which node P will be pulled high by transistor P_PU while node N is pulled low by transistor N_PD. Conversely, negative polarity half-cycles of the input signal, there will be some period within each PWM period during which node N will be driven high by transistor N_PU while node P is pulled low by transistor P_PD. These differential voltage pulses applied across load 11 will replicate the input signal as audible output, in the case where load 11 is an audio speaker.
It has been observed, however, that distortion is caused in this conventional arrangement as a result of the “dead time” enforced by drive circuits 9P, 9N. This distortion is especially noticeable at low amplitude input signal levels. FIG. 2 illustrates, by way of a timing diagram, the operation of conventional amplifier 2 in the event of such a low level audio signal. The time period illustrated in FIG. 2 corresponds to approximately one period of the reference ramp waveform REF output by generator 5. Prior to time t0 within this period, the instantaneous amplitude of the reference waveform REF from generator 5 is higher than both voltages on lines P_IN, N_IN, causing both comparators 6P, 6N to issue low output levels at nodes P_COMP, N_COMP, respectively. In turn, drive circuits 9P, 9N have both issued low-side drive signals active (“P-LS ACTIVE” and “N-LS ACTIVE”), turning on pull-down transistors P_PD, N_PD, respectively. At time t0, the instantaneous amplitude of the output of generator 5 falls below the voltage at node P_IN, resulting in a high-level output from comparator 6P at node P_COMP, while node N_COMP remains at a low level, reflecting the differential voltage output between nodes P_IN and N_IN from integrating differential amplifier 4. This high level at node P_COMP causes drive circuit 9P to turn off pull-down transistor P_PD. Because of dead-time DT enforced by drive circuit 9P, pull-up transistor P_PU is not immediately turned on, but both of transistors P_PU, P_PD are held off until dead-time DT elapses. At time t1, node N_IN exceeds the triangle amplitude, and comparator 6N issues a high level at its output node N_COMP. In response, drive circuit 9N turns off pull-down transistor N_PD, but turns on pull-up transistor N_PU only after dead time DT elapses.
The difference in time between node P_COMP going high (at time t0) and node N_COMP going high (at time t1) thus corresponds to the differential input voltage at inputs IN+, IN−. Ideally, this time differential would be reflected by a corresponding differential pulse across load 11, for example as shown by line ΔPN (desired) in FIG. 2. However, the combination of the dead-time DT and the non-ideal response of load 11 distorts the output pulse from its ideal duration that would correspond to the low-level differential input signal, as shown in FIG. 2. After time t1, when both of drive circuits 9P, 9N are in their dead-time, the voltage of nodes P and N across load 11 equalize, typically to ground by virtue of the load from source-drain capacitance. At time t2, when the P-side dead-time DT ends by drive circuit 9P turning on pull-up transistor P_PU (“P-HS ACTIVE” in FIG. 2), node N is still at a high-impedance state. The high-side drive from pull-up transistor P_PU pulling up node P at this time couples through load 11, and pulls up the voltage of node N, which is floating at this time. This coupling of the high-side drive through load 11 zeroes any differential signal that would have ideally been produced, as indicated by the duration labeled ERR in FIG. 2. Upon the N-side dead-time DT elapsing, at time t3, drive circuit 9N turns on its pull-up transistor N_PU (“N-HS ACTIVE”), which maintains nodes P and N across load 11 at the same high level.
The operation is similar in the second half of the PWM cycle, for the high-to-low transition of nodes P and N. Because the voltage at node N_IN is lower than that at node P_IN for this input signal level, node N_COMP at the output of comparator 6N makes a high-to-low transition at time t4, followed by the high-to-low transition of node P_COMP at time t5. However, drive circuit 9N again enforces dead-time DT. During the time between t4 and t5 that pull-up transistor P_PU remains on while drive circuit 9N is in its dead-time, the driving of node P high couples through load 11 to floating node N, eliminating any differential voltage to build up across load 11. This duration is also labeled in FIG. 2 as error ERR. Once both nodes N and P are at high-impedance states during the common dead-time between time t5 and t6, nodes N and P are at the same potential, shorted together by load 11. At time t6, the N drive dead-time DT elapses, following which pull-down transistor N_PD turns on (“N-LS ACTIVE”), pulling both of nodes N and P low; finally, at time t7, pull-down transistor P_PD is turned on as the P drive dead-time elapses (“P-LS ACTIVE”).
The combination of the dead-time DT with the short output pulse width for this low level input signal has the result of distorting the output drive applied to load 11. This distortion results from the coupling of the drive voltage from one side of load 11 (the P side, in this example) to the side of load 11 that is floating because of the high-impedance state at node N during its dead-time DT. This one-sided drive eliminates any differential signal across load 11. If dead-time DT were zero, the differential voltage across nodes P_IN, N_IN at the output of integrating differential amplifier 4 would be exactly reflected in the times during which node P_COMP was at a high level and node N_COMP was at a low level. In the example of FIG. 2, these times are the durations between time t2 and time t3, and between time t4 and time t5 during which the ideal differential voltage pulses at nodes P, N across load 11 are shown by “ΔPN (desired)”. However, the dead-times DT in the operation of the practical circuit of FIG. 2 prevent this differential voltage from appearing across load 11. In this extreme example, there is no time during the cycle at which node P is driven high while node N is pulled low. As a result, no differential pulse whatsoever appears across load 11 in this PWM cycle, as shown in FIG. 2 by the line “ΔPN (actual)”. The energy applied to load 11 therefore does not correspond to the level requested by the signal at the outputs of integrating differential amplifier 4.
Harmonic distortion results from this discrepancy between the output energy applied to load 11 and the desired input signal. FIG. 3 illustrates the result for a constant tone (single sinusoid) input signal at a frequency significantly lower than the PWM frequency of reference waveform generator 5. Ideal sinusoidal waveform 13 represents this tone without distortion, and thus represents the ideal case in which the output signal identically matches an input sinusoidal signal. Waveform 15 represents an example of the output waveform corresponding to energy applied to load 11 by a conventional circuit such as that described above relative to FIGS. 1 and 2. As evident at the zero-crossing point, the signal amplitude flattens because of the inability of that conventional circuit to apply energy to load 11 at low input signal levels. A similar flattening will occur as the output goes negative at the beginning of a negative polarity half-cycle of the input signal. In the case of an audio signal, this flattening of the sinusoid from the intended signal amounts to distortion.
Those skilled in the art will recognize that a shorter dead-time will lower the minimum signal level for which the circuit will produce a differential output signal to the load, and will also reduce the extent of the dead-time distortion. However, a shorter dead-time increases the possibility of damaging “crowbar” current being conducted through the push-pull output drivers. Such short dead-times are especially risky especially if the circuit is being manufactured in high quantities, considering the effects of process variations.
By way of further background, it has been observed, according to this invention, that distortion resulting from drive circuit dead-time also occurs at larger input signal amplitude levels. FIG. 9 illustrates an example of the manner in which distortion due to drive circuit dead-time occurs for large input signal amplitudes, over a positive half-cycle of the input signal. In this example, the input differential signal received at nodes IN+, IN− in amplifier 2 of FIG. 1 is reasonably large, as evident by the larger difference in time between the transition at node P_COMP (at time t0 in FIG. 9) and the transition at node N_COMP (time t2 in FIG. 9) than that difference shown in FIG. 2. More specifically, in the larger signal amplitude example of FIG. 9, this difference between comparator output transition times is larger than dead-time DT (which, for the P-side drive circuit 9P, runs from time t0 to time t1 in FIG. 9).
As shown in FIG. 9 and as mentioned above, the low-to-high transition at the output of comparator 6P occurs at time t0, which initiates the dead-time DT at node P, during which drive circuit 9P turns off both of transistors P_PU and P_PD. During this time, because the low-side drive N_LS is pulling node N low, the high impedance state of drive circuit 9P allows node P to be held low via load 11. Ideally, if no dead-time DT were enforced, drive circuit 9P would drive node P high beginning at time t0, establishing a differential voltage between nodes P and N beginning at time t0 and continuing until the transition of N_COMP at time t2. This ideal differential voltage pulse is shown on line ΔPN (desired) of FIG. 9, having a duration p. Instead, because of the dead-time DT, the differential voltage pulse ΔPN (actual) does not begin until time t1, continuing to time t2 (and thus having a duration of p-DT). At time t2, node N_COMP makes its low-to-high transition, initiating the dead-time at node N, allowing the high-side active drive at node P to pull up the voltage at node N via load 11. This ends the differential voltage across load 11.
A similar error in the differential voltage across load 11 occurs at the trailing transition in the latter half of the PWM cycle. At time t3, node N_COMP makes a high-to-low transition, again initiating the dead-time at node N. Because of the high-side active drive at node P, however, the voltage at node N remains high until the N-side dead-time elapses at time t4. Accordingly, at time t4, drive circuit 9N drives its low-side output N_LS active, turning on transistor N_PD and pulling node N low, while node P continues to be driven high by drive circuit 9P. This establishes a differential voltage across load 11 until time t5, at which time node P_COMP makes its high-to-low transition, allowing driven node N to pull down node P via load 11 during the P-side dead-time DT. Again, the ideal differential voltage pulse for this input signal level would run from time t3 to time t5 (duration P in FIG. 9); the dead-time DT reduces this differential voltage pulse to only run from time t4 to time t5. While the ideal PWM output pulse width would amount to 2p, the actual output pulse width is instead 2p-2DT—the actual output pulse width is distorted by twice the dead-time.
As such, it has been observed, according to this invention, that the provision of dead-time not only affects the low signal amplitude signals, but also reduces the fidelity of larger amplitude signals, as well.